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Freescale Semiconductor Technical Data
Document Number: MC33886 Rev 8.0, 2/2007
5.0 A H-Bridge
The 33886 is a monolithic H-Bridge ideal for fractional horsepower DC-motor and bi-directional thrust solenoid control. The IC incorporates internal control logic, charge pump, gate drive, and low RDS(ON) MOSFET output circuitry. The 33886 is able to control continuous inductive DC load currents up to 5.0 A. Output loads can be pulse width modulated (PWM-ed) at frequencies up to 10 kHz. A Fault Status output reports undervoltage, short circuit, and overtemperature conditions. Two independent inputs control the two half-bridge totem-pole outputs. Two disable inputs force the H-Bridge outputs to tri-state (exhibit high impedance). The 33886 is parametrically specified over a temperature range of -40C TA 125C, 5.0 V V+ 28 V. The IC can also be operated up to 40 V with derating of the specifications. The IC is available in a surface mount power package with exposed pad for heatsinking. Features * 5.0 V to 40 V Continuous Operation * 120 m RDS(ON) H-Bridge MOSFETs * TTL / CMOS Compatible Inputs * PWM Frequencies up to 10 kHz * Active Current Limiting via Internal Constant OFF-Time PWM (with Temperature-Dependent Threshold Reduction) * Output Short Circuit Protection * Undervoltage Shutdown * Fault Status Reporting * Pb-Free Packaging Designated by Suffix Code VW
33886
H-BRIDGE
VW SUFFIX (PB-FREE) DH SUFFIX 98ASH70702A 20-PIN HSOP
ORDERING INFORMATION
Device MC33886DH/R2 MC33886VW/R2 Temperature Range (TA) - 40C to 125C Package
20 HSOP
5.0 V CCP
33886 V+ OUT1
V+
IN MCU OUT OUT OUT OUT
FS IN1 IN2 D1 D2 OUT2 PGND AGND
MOTOR
Figure 1. 33886 Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products.
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM CCP VPWR CCP V+
Charge Pump
80 uA 80 A
(each)
5.0 V Regulator
Current Limit, Current Limit, Overcurrent Short Circuit Sense Sense Circuit Circuit OUT1 Gate Drive OUT2
OverOvertemperature temperature
IN1 IN2 D1 D2
25 A 25 uA
Control Logic
FS
Undervoltage
AGND
PGND
Figure 2. 33886 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
AGND FS IN1 V+ V+ OUT1 OUT1 DNC PGND PGND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
DNC IN2 D1 CCP V+ OUT2 OUT2 D2 PGND PGND
Figure 3. 33886 Pin Connections Table 1. 33886 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.
Pin Number 1 2 Pin Name AGND FS Formal Name Analog Ground Fault Status for HBridge Logic Input Control 1 Low-current analog signal ground. Open drain active Low Fault Status output requiring a pull-up resistor to 5.0 V. Definition
3 4, 5, 16 6, 7 8, 20
IN1 V+ OUT1 DNC
True logic input control of OUT1 (i.e., IN1 logic High = OUT1 logic High).
Positive Power Supply Positive supply connections. H-Bridge Output 1 Do Not Connect Output 1 of H-Bridge. Either do not connect (leave floating) or connect these pins to ground in the application. They are test mode pins used in manufacturing only. Device high-current power ground. Active Low input used to simultaneously tri-state disable both H-Bridge outputs. When D2 is logic Low, both outputs are tri-stated. Output 2 of H-Bridge.
9 -12 13
PGND D2
Power Ground Disable 2
14, 15 17 18
OUT2 CCP D1
H-Bridge Output 2
Charge Pump Capacitor External reservoir capacitor connection for internal charge pump capacitor. Disable 1 Active High input used to simultaneously tri-state disable both H-Bridge outputs. When D1 is logic High, both outputs are tri-stated. True logic input control of OUT2 (i.e., IN2 logic High = OUT2 logic High).
19
IN2
Logic Input Control 2
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Rating Supply Voltage Input Voltage (1) FS Status Output
(2)
Symbol V+ VIN V FS IOUT VESD1 VESD2
Value 40 -0.1 to 7.0 7.0 5.0
Unit V V V A V
Continuous Current (3) ESD Voltage for DH Package Human Body Model Machine Model (5) ESD Voltage for VW Package Human Body Model (4) Machine Model (5) Storage Temperature Ambient Operating Temperature Operating Junction Temperature Peak Package Reflow Temperature During Reflow
(8) (9) (7) (4)
2000 (6) 200 V
VESD1 VESD2 TSTG TA TJ , TPPRT RJB
2000 200 -65 to 150 -40 to 125 -40 to 150 Note 8. ~5.0 C C C C C/W
Approximate Junction-to-Board Thermal Resistance (and Package Dissipation = 6.0 W) (10) Notes 1. 2. 3. 4. 5. 6. 7. 8. 9.
Exceeding the input voltage on IN1, IN2, D1, or D2 may cause a malfunction or permanent damage to the device. Exceeding the pull-up resistor voltage on the open drain FS pin may cause permanent damage to the device. Continuous current capability so long as junction temperature is 150C. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ). ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). All pins are capable of Human Body Model ESD voltages of 2000 V with two exceptions pertaining only to the DH suffix package: (1) D2 to PGND is capable of 1500 V and (2) OUT1 to AGND is capable of 1000 V. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heatsinking. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics. Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual RJB (junction-to-PC board) values will vary depending on solder thickness and composition and copper trace.
10.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 5.0 V V+ 28 V and -40C TA 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER SUPPLY Operating Voltage Range (11) Standby Supply Current VEN = 5.0 V, IOUT = 0 A Threshold Supply Voltage Switch-OFF Switch-ON Hysteresis CHARGE PUMP Charge Pump Voltage V+ = 5.0 V 8.0 V V+ 40 V CONTROL INPUTS Input Voltage (IN1, IN2, D1, D2) Threshold High Threshold Low Hysteresis Input Current (IN1, IN2, D1) VIN = 0 V D2 Input Current (13) V D2 = 5.0 V I D2 - 25 100
(12)
Symbol
Min
Typ
Max
Unit
V+ IQ (standby)
5.0
-
40
V mA
-
-
20
V+(thres-OFF) V+(thres-ON) V+(hys)
4.15 4.5 150
4.4 4.75 -
4.65 5.0 -
V V mV
VCP - V+ 3.35 - - - - 20
V
V VIH VIL VHYS IIN -200 -80 - A 3.5 - 0.7 - - 1.0 - 1.4 - A
Notes 11. Specifications are characterized over the range of 5.0 V V+ 28 V. Operation > 28 V will cause some parameters to exceed listed min/max values. Refer to typical operating curves to extrapolate values for operation > 28 V but 40 V. 12. Inputs IN1, IN2, and D1 have independent internal pull-up current sources. 13. The D2 input incorporates an active internal pull-down current sink.
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions 5.0 V V+ 28 V and -40C TA 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER OUTPUTS (OUT1, OUT2) Output-ON Resistance (14) 5.0 V V+ 28 V, TJ = 25C 8.0 V V+ 28 V, TJ = 150C 5.0 V V+ 8.0 V, TJ = 150C Active Current Limiting Threshold (via Internal Constant OFF-Time PWM) (15) High-Side Short Circuit Detection Threshold Low-Side Short Circuit Detection Threshold Leakage Current (16) VOUT = V+ VOUT = GND Output FET Body Diode Forward Voltage Drop (17) IOUT = 3.0 A Switch-OFF Thermal Shutdown Hysteresis FAULT STATUS (18) Fault Status Leakage Current (19) V FS = 5.0 V Fault Status Set Voltage I FS = 300 A
(20)
Symbol
Min
Typ
Max
Unit
RDS(ON) - - - ILIM 5.2 ISCH ISCL IOUT(leak) - - VF - - 2.0 100 30 200 60 11 8.0 6.5 - - 7.8 - - 120 - - - 225 300
m
A
A A A
V
C TLIM THYS 175 - - 15 - -
I FS(leak) - V FS(LOW) - - 1.0 - 10
A
V
Notes 14. Output-ON resistance as measured from output to V+ and ground. 15. Product with date codes of December 2002, week 51, will exhibit the values indicated in this table. Product with earlier date codes may exhibit a minimum of 6.0 A and a maximum of 8.5 A. 16. Outputs switched OFF with D1 or D2. 17. Parameter is guaranteed by design but not production tested. 18. Fault Status output is an open drain output requiring a pull-up resistor to 5.0 V. 19. Fault Status Leakage Current is measured with Fault Status High and not set. 20. Fault Status Set Voltage is measured with Fault Status Low and set with I FS = 300 A.
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions 5.0 V V+ 28 V and -40C TA 125C unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions unless otherwise noted.
Characteristic TIMING CHARACTERISTICS PWM Frequency (21) Maximum Switching Frequency During Active Current Limiting Output ON Delay (23) V+ = 14 V Output OFF Delay (23) V+ = 14 V Output Rise and Fall Time
(24) (22)
Symbol
Min
Typ
Max
Unit
f PWM f MAX
t d (ON)
- -
- -
10 20
kHz kHz s
- t d (OFF) - tf , t r 2.0 ta tb trr t d (disable) 15 12 100 - - -
-
18 s
-
18 s
V+ = 14 V, IOUT = 3.0 A Output Latch-OFF Time Output Blanking Time Output FET Body Diode Reverse Recovery Time (25) Disable Delay Time
(26)
5.0 20.5 16.5 - - 4.0 1.0
8.0 26 21 - 8.0 - 5.0 s s ns s s ms
Short Circuit / Overtemperature Turn-OFF Time (27) Power-OFF Delay Time
t FAULT
t pod
Notes 21. The outputs can be PWM controlled from an external source. This is typically done by holding one input high while applying a PWM pulse train to the other input. The maximum PWM frequency obtainable is a compromise between switching losses and switching frequency. Refer to Typical Switching Waveforms, Figures 10 through 17, pp. 10-11. 22. The Maximum Switching Frequency during active current limiting is internally implemented. The internal control produces a constant OFF-time PWM of the output. The output load current effects the Maximum Switching Frequency. 23. Output Delay is the time duration from the midpoint of the IN1 or IN2 input signal to the 10% or 90% point (dependent on the transition direction) of the OUT1 or OUT2 signal. If the output is transitioning High-to-Low, the delay is from the midpoint of the input signal to the 90% point of the output response signal. If the output is transitioning Low-to-High, the delay is from the midpoint of the input signal to the 10% point of the output response signal. See Figure 4, page 8. 24. Rise Time is from the 10% to the 90% level and Fall Time is from the 90% to the 10% level of the output signal. See Figure 6, page 8. 25. Parameter is guaranteed by design but not production tested. 26. Disable Delay Time is the time duration from the midpoint of the D (disable) input signal to 10% of the output tri-state response. See Figure 5, page 8. 27. Increasing currents will become limited at ILIM. Hard shorts will breach the ISCH or ISCL limit, forcing the output into an immediate tristate latch-OFF. See Figures 8 and 9, page 9. Active current limiting will cause junction temperatures to rise. A junction temperature above 160C will cause the active current limiting to progressively "fold-back" (or decrease) to 2.5 A typical at 175C where thermal latch-OFF will occur. See Figure 7, page 8.
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TIMING DIAGRAMS
TIMING DIAGRAMS
VIN1, IN2 (V)
5.0 50% 0 50%
VOUT1, 2 (V)
VPWR
td(ON) 90%
td(OFF)
10% 0 TIME
Figure 4. Output Delay Time
5.0 V
0V
0
Figure 5. Disable Delay Time
VOUT1, 2 (V)
V PWR 90%
tf
tr 90% 10% 10%
0
Figure 6. Output Switching Time
IILIM, IOUTPUT CURRENT (A) MAX LIM, CURRENT (A)
6.5 6.6
2.5 Thermal Shutdown 160 175 T J, JUNCTION TEMPERATURE (o C)
Figure 7. Active Current Limiting Versus Temperature (Typical)
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TIMING DIAGRAMS
Diode Reverse Recovery Spikes Load Capacitance and/or Diode Reverse Recovery Spikes
IOUT IILOAD, OUTPUT CURRENT (A) OUT , , CURRENT (A)
8.0 6.5 PWM Active Current Current Limiting Limiting (See Figure 7) (See (See Figure6) 7) 0
or IN2 IN1 OR IN2 IN2 or IN1 IN1OR IN2
ISCL Short Circuit Detect Threshold Typ. Short Ckt. Detect Threshold for Low-Side FETs Typical Current Threshold Typ. Current Limit Limiting Threshold
Hard Short Detect and Latch-OFF Hard Short Detect and Latch-Off
INn, LOGIC IN
[1]
[0]
IN1 IN2 IN1 IN2
IN2 or IN1 IN2 OR
IN1 or IN2 IN2ORIN1
D1, LOGIC IN D2, LOGIC IN FS, LOGIC OUT SF
[1]
[0]
[1]
[0]
[1] Outputs Outputs Tristated Tri-stated [0] TIME Outputs Operational Outputs Operational (per Input Control Condition) (per Input Control Condition)
Outputs Tristated Tri-stated
Figure 8. Active Current Limiting Versus Time
ILOAD, OUTPUT CURRENT (A) IOUT, CURRENT (A)
8.0 ta 6.5 tb
IShort Circuit Detect Threshold Overcurrent Minimum Threshold SCL Short Circuit Detect Threshold ta = Tristate Latch-OFF Time a = Output Output OFF Time ttb = Current Blanking Time b = Output Limit Blank Time Typical Current Typical PWM Load Limiting Waveform Current Limiting Waveform Hard Output Hard Short Detect Short Latch-OFF Latch-Off Prevented During tb TIME
Figure 9. Active Current Limiting Detail
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TYPICAL SWITCHING WAVEFORMS
TYPICAL SWITCHING WAVEFORMS
Important For all plots, the following applies: Ch2 = 2.0 A per division LLOAD = 533 H @ 1.0 kHz LLOAD = 530 H @ 10.0 kHz RLOAD = 4.0
* * * *
Output Voltage (OUT1)
Output Voltage (OUT1)
IOUT
Input Voltage (IN1)
IOUT
V+=34 V
fPWM =1.0 kHz
Duty Cycle=90%
Input Voltage (IN1)
V+=24 V fPWM =1.0 kHz Duty Cycle=10%
Figure 12. Output Voltage and Current vs. Input Voltage at V+ = 34 V, PMW Frequency of 1.0 kHz, and Duty Cycle of 90%, Showing Device in Current Limiting Mode
Figure 10. Output Voltage and Current vs. Input Voltage at V+ = 24 V, PMW Frequency of 1.0 kHz, and Duty Cycle of 10%
Output Voltage (OUT1)
IOUT
Output Voltage (OUT1)
Input Voltage (IN1)
IOUT
V+=22 V
fPWM =1.0 kHz
Duty Cycle=90%
Input Voltage (IN1)
V+=24 V fPWM =1.0 kHz Duty Cycle=50%
Figure 13. Output Voltage and Current vs. Input Voltage at V+ = 22 V, PMW Frequency of 1.0 kHz, and Duty Cycle of 90%
Figure 11. Output Voltage and Current vs. Input Voltage at V+ = 24 V, PMW Frequency of 1.0 kHz, and Duty Cycle of 50%
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TYPICAL SWITCHING WAVEFORMS
Output Voltage (OUT1)
Output Voltage (OUT1)
IOUT IOUT
Input Voltage (IN1)
V+=24 V fPWM =10 kHz Duty Cycle=50%
Input Voltage (IN1)
V+=12 V fPWM =20 kHz Duty Cycle=50%
Figure 14. Output Voltage and Current vs. Input Voltage at V+ = 24 V, PMW Frequency of 10 kHz, and Duty Cycle of 50%
Figure 16. Output Voltage and Current vs. Input Voltage at V+ = 12 V, PMW Frequency of 20 kHz, and Duty Cycle of 50% for a Purely Resistive Load
Output Voltage (OUT1)
Output Voltage (OUT1)
IOUT
IOUT
Input Voltage (IN1)
V+=24 V fPWM =10 kHz Duty Cycle=90%
Input Voltage (IN1)
V+=12 V fPWM =20 kHz Duty Cycle=90%
Figure 15. Output Voltage and Current vs. Input Voltage at V+ = 24 V, PMW Frequency of 10 kHz, and Duty Cycle of 90%
Figure 17. Output Voltage and Current vs. Input Voltage at V+ = 12 V, PMW Frequency of 20 kHz, and Duty Cycle of 90% for a Purely Resistive Load
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TYPICAL SWITCHING WAVEFORMS
Table 5. Truth Table The tri-state conditions and the fault status are reset using D1 or D2. The truth table uses the following notations: L = Low, H = High, X = High or Low, and Z = High impedance (all output power transistors are switched off).
Input Conditions Device State Fault Status Flag Output States
D1 Forward Reverse Freewheeling Low Freewheeling High Disable 1 (D1) Disable 2 (D2) IN1 Disconnected IN2 Disconnected D1 Disconnected D2 Disconnected Undervoltage
(28)
D2 H H H H X L H H X Z X X X
IN1 H L L H X X Z X X X X X X
IN2 L H L H X X X Z X X X X X
FS H H H H L L H H L L L L L
OUT1 H L L H Z Z H X Z Z Z Z Z
OUT2 L H L H Z Z X H Z Z Z Z Z
L L L L H X L L Z X X X X
Overtemperature (29) Short Circuit
(29)
Notes 28. In the case of an undervoltage condition, the outputs tri-state and the fault status is set logic Low. Upon undervoltage recovery, fault status is reset automatically or automatically cleared and the outputs are restored to their original operating condition. 29. When a short circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF independent of the input signals and the fault status flag is set logic Low.
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ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
0.40
0.35
0.30
0.25
Ohms
0.20 0.15
0.10
0.05
0.0
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
Volts
Figure 18. Typical High-Side RDS(ON) Versus V+
0.13 0.128 0.126
Ohms OHMS
0.124
0.122
0.12 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41
Volts VPWR
Figure 19. Typical Low-Side RDS(ON) Versus V+
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ELECTRICAL PERFORMANCE CURVES
9.0
8.0
7.0
6.0
milliOHMS amperes
5.0
4.0
3.0
2.0
1.0
0.0
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
Volts VPWR
Figure 20. Typical Quiescent Supply Current Versus V+
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
Numerous protection and operational features (speed, torque, direction, dynamic braking, and PWM control), in addition to the 5.0 A current capability, make the 33886 a very attractive, cost-effective solution for controlling a broad range of fractional horsepower DC motors. A pair of 33886 devices can be used to control bipolar stepper motors in both directions. In addition, the 33886 can be used to control permanent magnet solenoids in a push-pull variable force fashion using PWM control. The 33886 can also be used to excite transformer primary windings with a switched square wave to produce secondary winding AC currents. As shown in Figure 2, Simplified Internal Block Diagram, page 2, the 33886 is a fully protected monolithic H-Bridge with Fault Status reporting. For a DC motor to run the input conditions need be as follows: D1 input logic Low, D2 input logic High, FS flag cleared (logic High), with one IN logic Low and the other IN logic High to define output polarity. The 33886 can execute dynamic braking by simultaneously turning on either both high-side MOSFETs or both low-side MOSFETs in the output H-Bridge; e.g., IN1 and IN2 logic High or IN1 and IN2 logic Low. The 33886 outputs are capable of providing a continuous DC load current of 5.0 A from a 40 V V+ source. An internal charge pump supports PWM frequencies up to 10 kHz. An external pull-up resistor is required for the open drain FS pin for fault status reporting. Two independent inputs (IN1 and IN2) provide control of the two totem-pole half-bridge outputs. Two disable inputs (D1 and D2) are for forcing the H-Bridge outputs to a high impedance state (all H-Bridge switches OFF). The 33886 has undervoltage shutdown with automatic recovery, active current limiting, output short-circuit latchOFF, and overtemperature latch-OFF. An undervoltage shutdown, output short circuit latch-OFF, or overtemperature latch-OFF fault condition will cause the outputs to turn OFF (i.e., become high impedance or tri-stated) and the fault output flag to be set Low. Either of the Disable inputs or V+ must be "toggled" to clear the fault flag. The short circuit / overtemperature shutdown scheme is unique and best described as using a junction temperaturedependent active current "fold back" protection scheme. When a short circuit condition is experienced, the current limited output is "ramped down" as the junction temperature increases above 160C, until at 175C the current has decreased to about 2.5 A. Above 175C, overtemperature shutdown (latch-OFF) occurs. This feature allows the device to remain in operation for a longer time with unexpected loads, while still retaining adequate protection for both the device and the load.
FUNCTIONAL PIN DESCRIPTION POWER/ANALOG GROUNDS (PGND AND AGND)
Power and analog ground pins. The power and analog ground pins should be connected together with a very low impedance connection.
FAULT STATUS (FS)
This pin is the device fault status output. This output is an active Low open drain structure requiring a pull-up resistor to 5.0 V. Refer to Table 5, Truth Table, page 12.
POSITIVE POWER SUPPLY (V+)
V+ pins are the power supply inputs to the device. All V+ pins must be connected together on the printed circuit board with as short as possible traces offering as low impedance as possible between pins. V+ pins have an undervoltage threshold. If the supply voltage drops below a V+ undervoltage threshold, the output power stage switches to a tri-state condition and the fault status flag is set and the Fault Status pin voltage switched to a logic Low. When the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input pins and the fault status flag is automatically reset logic High.
LOGIC INPUT 1, 2 AND DISABLE1, 2 (IN1, IN2, D1, AND D2)
These pins are input control pins used to control the outputs. These pins are 5.0 V CMOS-compatible inputs with hysteresis. The IN1 and IN2 independently control OUT1 and OUT2, respectively. D1 and D2 are complimentary inputs used to tri-state disable the H-Bridge outputs. When either D1 or D2 is set (D1 = logic High or D2 = logic Low) in the disable state, outputs OUT1 and OUT2 are both tri-state disabled; however, the rest of the device circuitry is fully operational and the supply IQ (standby) current is reduced to a few milliamperes. Refer to Table 5, Truth Table, and Static Electrical Characteristics table, page 5.
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
H-BRIDGE OUTPUT 1, 2 (OUT1 AND OUT2)
These pins are the outputs of the H-Bridge with integrated output FET body diodes. The bridge output is controlled using the IN1, IN2, D1, and D2 inputs. The outputs have active current limiting above 6.5 A. The outputs also have thermal shutdown (tri-state latch-OFF) with hysteresis as well as short circuit latch-OFF protection. A disable timer (time t b) incorporated to detect currents that are higher than active current limit is activated at each
output activation to facilitate detecting hard output short conditions (see Figure 9, page 9).
CHARGE PUMP CAPACITOR (CCP)
Charge pump output pin. A filter capacitor (up to 33 nF) can be connected from the CCP pin and PGND. The device can operate without the external capacitor, although the CCP capacitor helps to reduce noise and allows the device to perform at maximum speed, timing, and PWM frequency.
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FUNCTIONAL DEVICE OPERATION FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DEVICE OPERATION
SHORT CIRCUIT PROTECTION
If an output short circuit condition is detected, the power outputs tri-state (latch-OFF) independent of the input (IN1 and IN2) states, and the fault status output flag is set logic Low. If the D1 input changes from logic High to logic Low, or if the D2 input changes from logic Low to logic High, the output bridge will become operational again and the fault status flag will be reset (cleared) to a logic High state. The output stage will always switch into the mode defined by the input pins (IN1, IN2, D1, and D2), provided the device junction temperature is within the specified operating temperature.
OVERTEMPERATURE SHUTDOWN AND HYSTERESIS
If an overtemperature condition occurs, the power outputs are tri-state (latched-OFF) independent of the input signals and the fault status flag is set logic Low. To reset from this condition, D1 must change from logic High to logic Low, or D2 must change from logic Low to logic High. When reset, the output stage switches ON again, provided that the junction temperature is now below the overtemperature threshold limit minus the hysteresis. Note Resetting from the fault condition will clear the fault status flag.
ACTIVE CURRENT LIMITING
The maximum current flow under normal operating conditions is internally limited to ILIM (5.2 A to 7.8 A). When the maximum current value is reached, the output stages are tri-stated for a fixed time (t a) of 20 s typical. Depending on the time constant associated with the load characteristics, the current decreases during the tri-state duration until the next output ON cycle occurs (see Figures 9 and 12, page 9 and page 10, respectively). The current limiting threshold value is dependent upon the device junction temperature. When -40C < TJ < 160C, ILIM is between 5.2 A and 7.8 A. When TJ exceeds 160C, the ILIM current decreases linearly down to 2.5 A typical at 175C. Above 175C the device overtemperature circuit detects TLIM and overtemperature shutdown occurs (see Figure 7, page 8). This feature allows the device to remain operational for a longer time but at a regressing output performance level at junction temperatures above 160C.
MAIN DIFFERENCES COMPARED TO MC33186DH1
* COD pin has been removed. Pin 8 is now a Do Not Connect (DNC) pin. * Pin 20 is no longer connected in the 20 HSOP package. It is now a DNC pin. * RDS(ON) max at TJ = 150C is now 225 m per each output transistor. * Maximum temperature operation is now 160C, as minimum thermal shutdown temperature has increased. * Current regulation limiting foldback is implemented above 160C TJ. * Thermal resistance junction to case has been increased from ~2.0C/W to ~5.0C/W.
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FUNCTIONAL DEVICE OPERATION PERFORMANCE
PERFORMANCE
The 33886 is designed for enhanced thermal performance. The significant feature of this device is the exposed copper pad on which the power die is soldered. This pad is soldered on a PCB to provide heat flow to ambient and also to provide thermal capacitance. The more copper area on the PCB, the better the power dissipation and transient behavior will be. Example Characterization on a double-sided PCB: bottom side area of copper is 7.8 cm2; top surface is 2.7 cm2 (see Figure 21); grid array of 24 vias 0.3 mm in diameter. Figure 22 shows the thermal response with the device soldered on to the test PCB described in Figure 21.
100
10
Rth (C/W) 1
0,1 0,001
0,01
0,1
1
10 t, Time (s)
100
1000
10000
Figure 22. 33886 Thermal Response
Top Side
Bottom Side
Figure 21. PCB Test Layout
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
A typical application schematic is shown in Figure 23. For precision high-current applications in harsh, noisy environments, the V+ by-pass capacitor may need to be substantially larger.
DC MOTOR V+ 33886 AGND V+ CCP 33 nF
+
47 F
OUT1
OUT2 D2 D1 FS
PGND
IN1 IN2
IN2 IN1 FS D1 D2
Figure 23. 33886 Typical Application Schematic
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Analog Integrated Circuit Device Data Freescale Semiconductor
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
Important For the most current revision of the package, visit www.freescale.com and perform a keyword search on 98ASH70702A listed below.
DH SUFFIX VW (Pb-FREE) SUFFIX 20-PIN HSOP PLASTIC PACKAGE 98ASH70702A ISSUE A
PIN ONE ID
h X 45 _ E2
1 20
E3
D
e/2
D1
10
11
B
EXPOSED HEATSINK AREA
E1
10X
E bbb Y A A2
M
A CB H
DATUM PLANE
E4 BOTTOM VIEW
NOTES: 1. CONTROLLING DIMENSION: MILLIMETER. 2. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.150 PER SIDE. DIMENSIONS D AND E1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE TIEBAR PROTRUSIONS. ALLOWABLE TIEBAR PROTRUSIONS ARE 0.150 PER SIDE. MILLIMETERS MIN MAX 3.000 3.400 0.100 0.300 2.900 3.100 0.00 0.100 15.800 16.000 11.700 12.600 0.900 1.100 13.950 14.450 10.900 11.100 2.500 2.700 6.400 7.200 2.700 2.900 0.840 1.100 0.350 BSC 0.400 0.520 0.400 0.482 0.230 0.320 0.230 0.280 1.270 BSC --- 1.100 q 0_ 8_ aaa 0.200 bbb 0.100 DIM A A1 A2 A3 D D1 D2 E E1 E2 E3 E4 L L1 b b1 c c1 e h
D2
18X
e
b1 c C
SEATING PLANE
GAUGE PLANE
SECTION W-W L1 W L (1.600) W
A1 A3
bbb C
q
DETAIL Y
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20
EEE CCC EEE CCC
b aaa
M
c1
CA
Analog Integrated Circuit Device Data Freescale Semiconductor
5.0 A H-BRIDGE THERMAL ADDENDUM - REVISION 2.0
5.0 A H-BRIDGE
33886
THERMAL ADDENDUM - REVISION 2.0
Introduction This thermal addendum is provided as a supplement to the MC33186 technical data sheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the data sheet. Packaging and Thermal Considerations The MC33186 is offered in a 20 pin HSOP exposed pad, single die package. There is a single heat source (P), a single junction temperature (TJ), and thermal resistance (RJA). TJ
=
20-PIN HSOP-EP
RJA
.
P
DH SUFFIX VW (Pb-FREE) SUFFIX 98ASH70702A 20-PIN HSOP-EP Note For package dimensions, refer to the 33886 device data sheet.
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an applicationspecific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Standards Table 6. Thermal Performance Comparison
[C/W]
Thermal Resistance
1.0 1.0 0.2
RJA(1)(2) RJB(2)(3) RJA(1)(4) RJC NOTES:
(5)
20 6.0 52 1.0
0.2 * All measurements are in millimeters Soldermast openings Thermal vias connected to top buried plane
1.Per JEDEC JESD51-2 at natural convection, still air condition. 2.2s2p thermal test board per JEDEC JESD51-5 and JESD51-7. 3.Per JEDEC JESD51-8, with the board temperature on the center trace near the center lead. 4.Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5.Thermal resistance between the die junction and the exposed pad surface; cold plate attached to the package bottom side, remaining surfaces insulated.
20 Terminal HSOP-EP 1.27 mm Pitch 16.0 mm x 11.0 mm Body 12.2 mm x 6.9 mm Exposed Pad
Figure 24. Thermal Land Pattern for Direct Thermal Attachment According to JESD51-5
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5.0 A H-BRIDGE THERMAL ADDENDUM - REVISION 2.0
A
AGND FS IN1 V+ V+ OUT1 OUT1 DNC PGND PGND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DNC IN2 D1 CCP V+ OUT2 OUT2 D2 PGND PGND
33886 Pin Connections 20-Pin HSOP
1.27 mm Pitch 16.0 mm x 11.0 mm Body 12.2 mm x 6.9 mm Exposed Pad
Figure 25. Thermal Test Board Device on Thermal Test Board Material: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air Table 7. Thermal Resistance Performance
Area A (mm2) C/W
Thermal Resistance
Outline:
RJA
0.0 300 600
52 36 32 10 7.0 6.0
Area A: Ambient Conditions:
RJS
0.0 300 600
RJA is the thermal resistance between die junction and ambient air. RJS is the thermal resistance between die junction and the reference location on the board surface near a center lead of the package (see Figure 25).
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Analog Integrated Circuit Device Data Freescale Semiconductor
5.0 A H-BRIDGE THERMAL ADDENDUM - REVISION 2.0
Thermal Resistance [C/W]
60 50 40 30
x
20 10 0
RJA
0
300 Heat spreading area A [mm]
600
Figure 26. Device on Thermal Test Board RJA
100 Thermal Resistance [C/W]
x
10
RJA
1
0.1
1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04 time[s] Time(s)
Figure 27. Transient Thermal Resistance RJA Device on Thermal Test Board Area A = 600 (mm2)
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Analog Integrated Circuit Device Data Freescale Semiconductor
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REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
7.0
7/2005
* * * * *
Implemented Revision History page Added Thermal Addendum Converted to Freescale format Updated data sheet format Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings on page 4. Added note with instructions to obtain this information from www.freescale.com.
8.0
2/2007
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Analog Integrated Circuit Device Data Freescale Semiconductor
How to Reach Us:
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Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc., 2007. All rights reserved.
MC33886 Rev 8.0 2/2007

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